Chip floorplanning has long been a notorious bottleneck in semiconductor design, where automated tools often stumble, requiring veteran engineers to step in and fix the mess. Commercial software frequently generates crude layouts that require extensive manual refinement. Researchers Andrew B. Kahng, Sayak Kundu, and Bodhisatta Pramanik have tackled this challenge by introducing the Macro Placement Agentic Engine (MAGE)—a system of multimodal agents that mimic human reasoning rather than simply replicating patterns from training datasets.
Instead of feeding neural networks gigabytes of labeled data, MAGE relies on the encoding of expert engineering knowledge.
Its six-phase workflow utilizes text-based directives and design rules. These agents analyze the chip's structure, group macros, and perform visual audits based on logical inference. This approach eliminates the "black box" problem typical of traditional AI: every step taken by an agent is interpretable and verifiable.
Key Components of the MAGE Architecture
Text Directives: Utilizing natural language to communicate complex engineering constraints. Tournament Evaluation: Selecting the optimal placement through a competitive system between multiple agents. Human-like Metrics: Accounting for notches, whitespace, and component alignment. Multimodality: Combining graphical schematic analysis with logical specifications.
Of particular interest is the tournament-style evaluation system. Moving beyond standard PPA (Power, Performance, Area) metrics, which often overlook structural integrity, MAGE introduces four "human-centric" criteria: notch, whitespace, pocket, and alignment scores. In tests using NanGate45 and GlobalFoundries 12nm processes, the system showed dramatic improvements: Worst Negative Slack (WNS) improved by 11–19%, while Total Negative Slack (TNS) plummeted by 70–74% compared to leading commercial solutions.
In several scenarios, MAGE actually outperformed human experts, enhancing WNS by 18.3% while maintaining optimal wire length and power consumption. For tech leads, this is a major signal: the era of brute-force model training is giving way to architectures capable of applying specialized knowledge to new tasks without retraining. It appears that senior designers manually correcting macro placements will soon be as much of an anachronism as drawing schematics on a drafting table.